Build Your Career at Microscale

Location: Bangalore:

Experience: 3 to 12 Years.

Role:- Lead the algorithms team & deliver performing algorithms under all 3GPP defined scenarios

Requirements:-

• * Wireless technology exposure, especially OFDM based technologies
• * Good wireless & DSP fundamentals
• * hands on experience in implementation of receiver algorithm like CFO correction, timing offset estimate, PSS and SS search, channel estimate LS, MMSE, equalisation
• * Should have understanding of RF impairments and their redressal mechanism in baseband in RF
• * Good skills in interpreting 3GPP specs & identifying need for algorithms
• * Extensive experience in developing/evaluating algorithms for OFDM based systems Must be good in Matlab & in C

Job Description

• + Understand the 3GPP requirements related to L1 procedures & channels performance
• + Make a list of requirements applicable to Alif modem
• + Design L1 algorithms & verify in matlab to evaluate compliance to performance requirements
• + Define and track activities related to improving the performance
• + Define KPI's for L1 procedures & channels
• + Support for L1 performance testing (36.521-1, Section 8)
• + Figure out reason for failures after discussing with team and translate them into algorithm enhancement applicable to the concerned block

Location: Bangalore:

Experience: 3 to 7 Years.

Role:- RRC Developer to deliver features under 3GPP defined scenarios

Requirements:-

• * Preferable to have development experience in LTE RRC, PHY Interface
• * Preferable to have good knowledge in LTE architecture and other layers of LTE
• * Good in C, Linux and RTOS concepts
• * Good analytical skills
• * Good in usage of NW simulators, host test environments
• * Good knowledge in GIT
• * Good knwoledge in gdb or any other debugging tools
• * Qualification: one of the following: B.E, BTech, M.E, M.Tech

Job Description

• + Development and maintenance of RRC layer of Cat 4, Cat M1, Cat NB1 LTE protocol stacks

Location: Bangalore:

Experience: 6 to 15 Years.

Role:- BSP and driver development

Requirements:-

• * A good understanding on any RTOS/OS like ThreadX, FreeRTOS, Linux
• * Familiar with device driver development for one or more devices Serial/I2C/SPI/USB/Networking/Video/Audio/CAN/ etc
• *Sound knowledge on Microcontrollers/Microprocesors, ARM MPU (ARMv7/ARMv8) architectures
• * Should have experience in Linux Internal or RTOS(Preferably Theadx) – IPC (Message Queues, Shared memory, Semaphores), multithreading, Mutex, etc).
• * Good Experience in FPGA/SoC Board bring up from bootloader to Root files system mounting, including hands-on experience with lab instruments like oscilloscopes, waveforms analyzers
• * Experience in driver development for Linux or RTOS. Device Drivers Like USB, Ethernet, SD/MMC, ALSA, FB Drivers.
• * Good Knowledge of Yocto and Git tool, JIRA,
• * Familiarity with any IDE like ARM-DS, Keil, IAR, etc
• * Familiarity with any assembly instructions set
• * Experience with hardware debugger tools like Lauterbach, ULINK, JLINK, BDI
• * Experience with software development life cycle
• * Excellent problem-solving and analytical skills
• * Bachelor’s or Master degree or foreign degree equivalent in electrical, electronics engineering, computer science, information technology or a related technical field.
• * Experience with software development life cycle
• * A self-managed individual with Excellent problem-solving skills and Mentor the Junior Engineers

Job Description

• + Development of Device Drivers for Linux/ThreadX/FreeRTOS

Location: Bangalore:

Experience :-

• 1 : Experience Software Development or Test Automation in one of the following programming languages: Python/Perl/C/C++/Java (Python preferred).
• 2 : Experience using virtualization technologies such as VMware, Hyper-V, or KVM
• 3 : Experience testing a "systems" product (file systems/storage systems/databases/operating systems/hypervisors, or networking).
• 4 : Experience in CI/CD pipelines, monitoring, provisioning, and configuration management
• 5 : Comfortable with Docker, Kubernetes, and supporting technologies

Location: Bangalore:

Experience:3 to 8 Years.

Role:- Post silicon validation engineer

Job Function:-

Responsibilities for this position include validation and debug of new chip functionality, work with software teams to evaluate integrated system performance, test and characterize HW/SW interaction, device performance over voltage , process and operating conditions, and work with the production test teams to develop effective screens in production testing for system level issues. The position revolves around developing automated solutions for execution of System Level Test use cases, performance benchmarking especially for high end Snap dragon processors, graphics processors, high speed interfaces and modems and/or working with engineering teams for early-stage silicon bring-up and post-silicon validation efforts.

Responsibilities:-

ARM System-On-Chip and Post-Silicon ASIC Validation experience related to board bring up and debug.

• *Development of Bootloader stage for automated test suite.
• * Test content development in C using ARM compiler tool chains.
• *C test debugging and Silicon debugging on development platforms.
• * Providing test suite to deploy on different production sites.
• * Create validation suite and build automation.
• * Porting test cases in test automation tool, and ensuring proper test sequence, test execution and log failures.
• * Development of directed, random, and pseudo-random diagnostics for validation in compliance with Silicon spec and use cases
• * SW build loading and testing on the Automated tester hardware
• * Debug of diagnostics on various platforms using JTAG, Logic Analyzers, Oscilloscopes and similar equipment

Skills/Experience

• + Strong C programming
• + SoC Validation
• + V7/V8 architectures like ARM Cortex-M, ARM Cortex-A7, ARM Cortex A53/A57
• + Bootloaders, Linux kernel
• + Hands-on debugging experience with JTAG Lauterbach / Trace32 is required
• + Experienced in debugging production failures.

Good to have:

• + Linux kernel development
• + .NET programming
• + Python scripting

Location: Bangalore:

Experience:2-15Yrs.

Skills:-

• *2-8 years of hands-on experience in Physical Design domain from RTL to GDSII or Netlist to GDSII.
• *Block level Timing Signoff using industry standard Signoff tools..
• * Block level Physical Signoff (DRC, LVS, Antenna, IR) using industry standard Signoff tools.
• * Good Concepts of Digital Design and different stages of Physical Design.
• * Able to provide technical guidance to Junior Engineers..
• * Very good debugging skills
• * Scripting for flow automation using Tcl/perl/Awk/Shell
• * Ability to work independently on PD flow enhancement,
• * Technically sound & good team player
• * Good in Client communication.
• * Taped out 3-5 chips.
• * Good knowledge of VLSI process and device characteristics.
• * Experience doing physical design targeted to the 7nm/16nm FinFet process.
• * Good knowledge of cell libraries various views and models.
• * Good understanding of static timing analysis (STA), EM/IR and sign-off.
• * Strong hands-on experience with: Chip Level / Sub-chip level floor planning, partition, pin assignment, Power planning, Bump Planning, Pad Ring Creation, Block level physical implementation, timing closure, physical verification, Chip level integration of different sub-blocks and custom macros/IPs, Timing, IR/EM analysis and closure, Physical Verification block and chip level.
• * EDA Tool Expertise: Innovus, Tempus/PrimeTime-SI, Voltus/RedHawk, StarXT/Quantus, Calibre,LEC etc.

Location: Bangalore:

Experience: 3+ years

Skills:-

• * 3+ years in IP/SoC Level Verification
• *Languages: Verilog, System Verilog, C, Assembly.
• * Methodology: UVM (preferred), OVM, VMM.
• * IP Protocols : PCIE, DDR, USB, Ethernet, HDMI,MIPI etc..
• * Scripting : Perl/TCL/PYTHON.
• *Good understanding on Processor/DSP/GLS verification
• * Experienced in developing test bench components, writing tests and coverage tuning
• *Digital Design and Verification Verilog/System-verilog

Location: Bangalore:

Experience: 3+ years

Skills:-

• *Hands on experience with DFT 3-15 Years
• *Should have experience in DFT and ATPG activities on SoC designs with expertise in MBIST Planning/Insertion, Partitioning Design for Scan, Scan Insertion
• * Compression, Wrapper Insertion, ATPG Simulations.
• * Expertise in handling Flat/Hierarchical SoC designs
• * Expertise in JTAG, Boundary Scan, STA Constraints creation for DFT modes
• *Proven knowledge of VHDL & Verilog, RTL design and micro-architecture skills
• *Sound knowledge of tools/methodology (Industry standard Simulators and Accelerators, Synthesis, linting checks etc)